With development of mobile communications, a communications system has been developed from a single carrier system to a multicarrier system, and frequency-selective processing for a carrier is completed by using a digital intermediate frequency technology, which also becomes a common technology in the current communications field.
With arrival of a mobile broadband (MBB) era, radio access evolves from fourth generation (4G) to fifth generation (5G), a quantity of antennas of the system rises from 1 or 2 to 64-128,a bandwidth rises from 20 megahertz (MHz) to 1000 MHz; therefore, it is required to consider an effective up- and down-frequency conversion circuit technology that is suitable for a 5G era.
FIG. 1 shows a multicarrier intermediate frequency chain in wireless communications. A main receiving process in an upstream direction is as follows: a radio frequency air interface signal is received by an antenna; the signal is successively filtered by a duplex filter (DUP), amplified by a low-noise amplifier (LNA), and frequency-converted by a demodulator (DEMOD) to obtain a signal on an intermediate frequency; a digital intermediate frequency signal is output by using a high-precision analog-to-digital converter (ADC) to perform sampling on the signal; a low-speed baseband signal is output by using a digital down converter (DDC) to perform signal frequency conversion and using a sampling rate converter (SRC) to perform sampling rate conversion respectively; and the low-speed baseband signal is transmitted back to a baseband processing unit by using an optical fiber. A main process in a downstream sending direction is as follows: after performing sampling rate conversion on a low-speed baseband signal, an SRC outputs a high-speed baseband signal; after performing frequency conversion on the high-speed baseband signal, a digital up converter (DUC) outputs a digital intermediate frequency signal; then the digital intermediate frequency signal is converted to an analog intermediate frequency signal by a digital-to-analog converter (DAC); and after being modulated by a modulator (MIXER), amplified by a power amplifier (PA), and filtered by a DUP successively, the analog intermediate frequency signal is changed to a radio frequency signal.
In some approaches, an implementation structure of a combination of a DDC and an SRC is used for signal down-conversion of converting a digital intermediate frequency signal to a baseband signal, and an implementation structure of a combination of a DUC and an SRC is used for signal up-conversion of converting a baseband signal to a digital intermediate frequency signal. That is, in some approaches, an implementation structure of a combination of an SRC with a DUC or DDC is used for both the signal up-conversion and the signal down-conversion. The combination of the DUC and the SRC is used as an example, generally, the DUC is implemented by using a Coordinate Rotation Digital Computer (CORDIC) and an improved manner of the CORDIC, and a structure principle of the CORDIC and the improved manner of the CORDIC is shown in FIG. 2, where input of a phase rotator is a frequency control word and a phase control word, and output is a rotation angle:φi+1=φi+ω+φinit where φinit represents an initial phase; φi represents a phase angle of current rotation; φi+1 represents a phase angle of next rotation; and ω represents a frequency control word.
A butterfly circuit is used to generate a sine (sin θ) and a cosine (cos θ) signal.
When an in-phase and quadrature (IQ) signal is input, multiplication of an original IQ signal and a cos+j*sin complex signal is implemented by using a complex multiplication circuit:Iout=Iin*cos θ−Qin*sin θ;Qout=Iin*sin θ+Qin*cos θ;where Iin and Qin are output of the complex multiplication circuit and are input original IQ signals, and sin θ and cos θ are a sine signal and a cosine signal that are generated by the butterfly circuit; therefore, the whole DUC outputs a digital frequency mixing signal, and when no IQ signal input, the DUC outputs the sine signal or the cosine signal.
Generally, a decimation half-band filter (HBF) or an interpolation HBF is used in an implementation structure of the SRC, and the HBF is a finite impulse response filter (FIR) with special coefficients, where a half of the coefficients are 0. An implementation principle of the HBF is shown in FIG. 3, where x(n) is an input signal, y(n) is output of the SRC, and h(n) is a coefficient of the filter.
However, an existing frequency conversion circuit is a single-stage frequency conversion; therefore, a numerically controlled oscillator (NCO) needs to be implemented on a high-multiple clock. However, a CORDIC algorithm used by the NCO needs to implement complex logic such as a multiplier and an adder to complete computation of various transcendental functions, and implementing the complex logic such as the multiplier and the adder on the high-multiple clock may make a hardware circuit more complex to a great extent; therefore, circuit resource costs of the frequency conversion circuit are increased.